1Learning Outcomes¶
TODO
TODO
🎥 Lecture Video
2Visuals¶
Figure 1:Putting it all together: what is the order in which we access things?
Figure 2:Full memory access workflow.
Figure 3:Example of address translation with TLB.
Figure 4:Example of address translation with TLB (page fault).
Figure 5:Example of address translation with TLB (update TLB and page table).
Table 1:Three address translation cases. Two cache misses may now occur: on the TLB and on the memory access itself.
| Case | Performance | TLB | Page Table |
|---|---|---|---|
| 1 | Best | Hit ✅ | Not visited |
| 2 | Worse | Miss ❌ | Hit (Page Table Entry Valid) ✅ |
| 3 | Worst | Miss ❌ | Miss (Page Fault) ❌ |